FIG. 1A is a plane plan view showing a conventional test pattern used for measuring a contact resistance of a via-hole formed in a semiconductor substrate. FIG. 1B is a cross-sectional view taken on line X—X in FIG. 1A.
The conventional test pattern (conductive pattern or wiring pattern) is used for measuring a contact resistance of a conductive material 5 formed inside a via hole 4, formed in a semiconductor substrate 1. The semiconductor substrate 1 includes an upper surface 2 and a lower (or bottom) surface 3. The via hole 4 is formed to pass through the semiconductor substrate 1.
The test pattern includes an upper wiring pattern 40 formed on the upper surface 2 of the semiconductor substrate 1 and a lower (or bottom) wiring pattern 50 formed on the lower surface 3 of the semiconductor substrate 1.
The upper wiring pattern 40 includes a pad (electrode) 41 to be in contact with a current supply probe, a pad 42 to be in contact with a voltage supply probe, and a contact pattern 43 to electrically connect the pads 41 and 42 to the conductive material 5. The pads 41 and 42 and contact pattern 43 is formed in united body on the upper surface 2 of the semiconductor substrate 1.
The lower wiring pattern 50 includes a pad (electrode) 51 to be in contact with a current supply probe, a pad 52 to be in contact with a voltage supply probe, and a contact pattern 53 to electrically connect the pads 51 and 52 to the conductive material 5. The pads 51 and 52 and contact pattern 53 is formed in united body on the lower surface 3 of the semiconductor substrate 1.
FIG. 2 is circuit diagram of the conventional test pattern, shown in FIGS. 1A and 1B.
As shown in FIG. 2, the pads 41 and 51 are in contact with probes P1 and P2, respectively, so that a predetermined amount of electric current I is supplied from a direct power supply (DC) to the pads, 41 and 51. The current I flows along a path formed by the probe P1, the pad 41, the conductive pattern 43, the conductive material 5, the conductive pattern, the pad 51 and the P2 in this order. As a result, a voltage, calculated by multiplying the current I and the contact resistance of the conductive material 5, is applied between the ends of the conductive material 5.
On the other hand, the pads 42 and 52 are in contact with probes P3 and P4, respectively. The voltage (potential) V applied between the pads 42 and 45 is measured by a voltage meter VM.
The voltage meter VM should have a high sensitivity so that the voltage V can be assumed to be the same as a voltage applied over the ends of the conductive material 5. Therefore, the contact resistance R of the conductive material 5 is calculated by the following equation: R=V/I
However, according to the above-described conventional test pattern, the pads 41 and 42 are arranged on the upper surface 2 of the semiconductor substrate 1 while the pads 51 and 52 are arranged on the lower surface 3 of the semiconductor substrate 1; and therefore, the probes P1 to P4 are required to be arranged in contact with the pads 41, 42, 51 and 52 from the both sides of the semiconductor substrate 1. As a result, it is required to use a specially-designed device for measuring or testing electrical characteristics of the semiconductor substrate 1.